Power Optimization using Low-Transition Rate based LFSR Pattern Generator

Abstract

Dynamic power dissipation has been increased exponentially with the excessive switching of nodes inside the digital electronic circuits. Power dissipation on these circuits are highly input pattern dependent. This work exploits the generation of efficient input patterns with the ability to reduce maximum switching activity in the circuit by using linear feedback shift register (LFSR) technique. This approach is further modified by the insertion of the low-transition density with highly correlated signals in the LFSR-based patterns. The transition between different patterns reduces the substantial amount of switching activity in the circuit. Reduction in transition results the low dynamic power consumption. Power consumption have been estimated by using standard ISCAS 85 and 89 benchmark circuits. The experimental results demonstrate that power can be significantly optimized using this approach.