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Please use this identifier to cite or link to this item: http://142.54.178.187:9060/xmlui/handle/123456789/18794
Title: Low-Power Integrated Circuit Design Optimization Approach
Authors: Y. A. Durrani
Keywords: Low-power
Power Optimization
Power Estimation
Issue Date: 4-Jan-2016
Publisher: Taxila: University of Engineering and Technology, Taxila
Citation: Durrani, Y. A. (2016). Low-power integrated circuit design optimization approach. Technical Journal, UET, Taxila, 21, 32-42.
Abstract: Abstract— In this tutorial survey, the paper presented a general review of the state-of-the-art techniques in optimizing the power dissipation on digital electronic systems. The source of power dissipation is focused on complementary metal-oxide-semiconductor (CMOS) circuits. This basic information cannot be implemented directly to optimize power dissipation due to the low abstraction level, but will be helpful to solve the power related problem. The major power factors are considered for the hardware and the software with the most rustful approaches of all levels of the design flow. The paper review is organized in three different types of digital system design: interpret conceptually, design flow, and management.
URI: http://142.54.178.187:9060/xmlui/handle/123456789/18794
ISSN: 2313-7770
Appears in Collections:Issue 01

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