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DC Field | Value | Language |
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dc.contributor.author | Y. A. Durrani | - |
dc.date.accessioned | 2023-03-14T05:00:07Z | - |
dc.date.available | 2023-03-14T05:00:07Z | - |
dc.date.issued | 2016-11-08 | - |
dc.identifier.citation | Durrani, Y. A. (2016). Design of High Performance IIR Filter Using Vedic Multiplication Method. University of Engineering and Technology Taxila. Technical Journal, 21(4), 50. | en_US |
dc.identifier.issn | 2313-7770 | - |
dc.identifier.uri | http://142.54.178.187:9060/xmlui/handle/123456789/18909 | - |
dc.description.abstract | filters can be found in most of the electronic circuits. One major application of these filters involve an input signals that are sampled and converted to the real-time signal to the modern computers. This paper describes the high performance infinite impulse response (IIR) filter using Vedic multiplication method due its low round-tY noise and low quantization errors. It reduces the computational delay and hardware to minimize the number of iterations and enhances the performance of the DSP processor. Vedic method enables the parallel processing stages of intermediate products and removes the unnecessary multiplication steps with zeros. The filter is designed on Xilinx software and different frequency responses are evaluated in Matlab at different filter orders. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Taxila: University of Engineering and Technology, Taxila | en_US |
dc.subject | Digital Filter | en_US |
dc.subject | Vedic Multiplication | en_US |
dc.subject | Frequency Responses | en_US |
dc.subject | Cascaded Structure | en_US |
dc.title | Design of High Performance IIR Filter Using Vedic Multiplication Method | en_US |
dc.type | Article | en_US |
Appears in Collections: | Issue 04 |
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8.%20Design%20of%20High%20Performance%20IIR%20filter%20Using%20Vedic%20Multiplication%20Method.htm | 219 B | HTML | View/Open |
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