Automatic Generation of Shared Hardware Design for Multiple Application Circuits

Abstract

Field Programmable Gate Arrays (FPGAs) are popular due to their programming flexibility and ease of design modification. However, the benefits of reconfigurability and reusability of FPGAs are also responsible for their inefficiencies compared to Application Specific Integrated Circuits (ASICs). FPGAs suffer huge gap in terms of area, power and speed as compared to ASICs. Despite their inefficiency, FPGAs are still replacing ASICs in mid and low-volume products. This thesis explores the design space between FPGA and ASIC. Several architectural modifications are proposed in the FPGA to get feasible architectures that lie between an ASIC and an FPGA. ThisthesisexploresthefeasibilityofSRAM-TablesharinginFPGAarchitectureswithlarger LUT sizes. SRAM-Table sharing based FPGA architecture allows sharing of SRAM-Table among NPN-equivalent functions, thus allowing reduction in the area as well as the numberofconfigurationbits.ToaccommodatethisconceptinexistingFPGAarchitecture,anew CLB architecture is proposed with LUT input sizes greater than four, higher degree of sharing, and more shared pairs. The CAD flow is also modified to efficiently map the netlists ontheproposedarchitecture.ExperimentalresultsonMCNCbenchmarkcircuitssuggestan overall area reduction of 7% while maintaining the same critical path delay and no compromise on FPGA programming flexibility. Manydigitalsystemsprovidemultiplebutcloselyrelatedfunctionalities,notallofthemare required simultaneously. Dedicated hardware solution for each functionality will waste too much silicon area. This work also explores shared hardware solution for a set of functionalities which will execute only one functionality at a time. The shared hardware solutions explored in this thesis are termed as ASIF++ and Multi-Circuit. A previously proposed technique named as Application Specific Inflexible FPGA (ASIF) is further enhanced to propose ASIF++. An ASIF is a customized design for a given set of application circuits, which is generated by significantly optimizing the routing resources ofanFPGA.ThisworkoptimizeslogicblocksofASIFusingSRAM-tablesharingtechnique. Moreover,SRAMsintheroutingnetworkareremovedbyapplyinggateinsertiontechnique. Thistechniquenotonlyreducesarea,butalsominimizesreconfigurationtime,bitstreamsize and size of external memory used to store circuit bitstreams. ASIF++ is 4∼9% area efficient than ASIF for group of 2-5 circuits. Thisthesisfurtherexploresthefeasibilityofsharedhardwaresolution.LogicblocksofASIF++ are further optimized to a shared hardware named as "Multi Circuit". It is a customized single platform shared ASIC for a known set of applications. Multi-circuit is primarily meant to be integrated as an embedded component in a larger design such as an SoC (System On Chip). Experiments reveal that Multi-Circuit is 73% ∼ 89% smaller than its corresponding FPGA design. Multi-Circuit is also 18%∼ 42% smaller than ASIF++. An automatic hardware generator is also presented that generates VHDL models of MultiCircuit and ASIF++, and bitstreams of the circuits mapped on them.